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? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? half-bridge gate drive ic fan73932 ? rev. 1.0.1 february 2010 fan73932 half-bridge gate drive ic features ? floating channel for bootstrap operation to +600v ? typically 2.5a/2.5a sourcing/sinking current driving capability ? extended allowable negative v s swing to -9.8v for signal propagation at v bs =15v ? high-side output in phase of in input signal ? 3.3v and 5v input logic compatible ? matched propagation delay for both channels ? built-in shutdown function ? built-in uvlo functions for both channels ? built-in common-mode dv/dt noise canceling circuit ? internal 400ns minimum dead-time applications ? high-speed power mosfet and igbt gate driver ? induction heating ? high-power dc-dc converter ? synchronous step-down converter ? motor drive inverter description the fan73932 is a half-bridge, gate-drive ic with shut- down and dead-time functions which can drive high- speed mosfets and igbts that operate up to +600v. it has a buffered output stage with all nmos transistors designed for high pulse current driving capability and minimum cross-conduction. fairchild?s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circum- stances. an advanced level-sh ift circuit offers high-side gate driver operation up to v s =-9.8v (typical) for v bs =15v. the uvlo circuit prevents malfunction when v dd and v bs are lower than the specified threshold voltage. the high-current and low-output voltage drop feature makes this device suitable for all kinds of half- and full- bridge inverters, like motor drive inverter, switching mode power supply, induction heating, and high-power dc-dc converter applications. ordering information for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . 8-sop part number package operating temperature range eco status packing method FAN73932M 8-sop -40c to +125c rohs tube FAN73932Mx ta p e & r e e l
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 typical appli cation diagrams figure 1. typical application circuit internal block diagram figure 2. functional block diagram +15v up to 600v pwm shutdown pwm ic control d boot c boot r boot lo com v b v s v dd in 7 ho 6 8 5 2 3 1 load +15v 4 sd uvlo driver pulse generator 5 3 8 6 in v dd com v b v s r r s q driver hs(on/off) ls(on/off) delay uvlo ho lo noise canceller 4 7 2 1 sd schmitt trigger input shoot though prevention dead-time { 400ns } 5v 200k
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 pin configuration figure 3. pin configuration (top view) pin definitions pin # name description 1 in logic input for high-side and low-side gate driver output, in-phase with ho 2sd logic input for shutdown 3 com ground 4 lo low-side driver return 5v dd supply voltage 6v s high-voltage floating supply return 7 ho high-side driver output 8v b high-side floating supply lo fan73932 in ho com v b v dd 1 2 3 4 8 7 6 5 sd v s
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. in addi- tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. t a =25c unless otherwise specified. notes: 1. mounted on 76.2 x 114.3 x 1.6mm pcb (fr-4 glass epoxy material). 2. refer to the following standards: jesd51-2: integral circuits thermal test method environmental conditions - natural convection; jesd51-3: low effective thermal conduc tivity test board for leaded surface mount packages 3. do not exceed p d under any circumstances. recommended oper ating conditions the recommended operating conditions table defines the conditions for actual dev ice operation. recommended operating conditions are specified to ensure optimal perfor mance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 4. shutdown (sd ) input is internally clamped with 5.2v. symbol parameter min. max. unit v b high-side floating supply voltage -0.3 625.0 v v s high-side floating offset voltage v b -25.0 v b +0.3 v v ho high-side floating output voltage v s -0.3 v b +0.3 v v lo low-side output voltage -0.3 v dd +0.3 v v dd low-side and logic fixed supply voltage -0.3 25.0 v v in logic input voltage (in) -0.3 v dd +0.3 v v sd logic input voltage (sd )-0.35.5v com logic ground and low-side driver return v dd -25.0 v dd +0.3 v dv s /dt allowable offset voltage slew rate 50 v/ns p d power dissipation (1, 2, 3) 0.625 w ja thermal resistance 200 c/w t j junction temperature +150 c t stg storage temperature -55 +150 c symbol parameter min. max. unit v b high-side floating supply voltage v s +10 v s +20 v v s high-side floating supply offset voltage 6-v dd 600 v v ho high-side output voltage v s v b v v dd low-side and logic fixed supply voltage 10 20 v v lo low-side output voltage com v dd v v in logic input voltage (in) com v dd v v sd logic input voltage (sd ) (4) com 5 v t a operating ambient temperature -40 +125 c
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 electrical characteristics v bias (v dd , v bs )=15.0v, com=0v, and t a = 25c, unless otherwise specified. the v in and i in parameters are referenced to com and are applicable to the respective input leads: in and sd . the v o and i o parameters are referenced to com and are applicable to th e respective output leads: ho and lo. note: 5 these parameters guaranteed by design. symbol parameter test condition min. typ. max. unit power supply section i qdd quiescent v dd supply current v in =0v, sd =5v 320 700 a i qbs quiescent v bs supply current v in =0v or 5v, sd =5v 50 120 a i pdd operating v dd supply current f in =20khz, no load, sd =5v 700 1300 a i pbs operating v bs supply current c l =1nf, f in =20khz, rms, sd =5v 420 800 a i sd shutdown mode supply current sd =0v, sd =5v 400 800 a i lk offset supply leakage current v b =v s =600v 10 a bootstrapped supply section v dduv+ v bsuv+ v dd and v bs supply under-voltage positive going th reshold voltage v dd =v bs =sweep 8910v v dduv- v bsuv- v dd and v bs supply under-voltage negative going threshold voltage v dd =v bs =sweep 7.4 8.4 9.4 v v dduvh- v bsuvh v dd and v bs supply under-voltage lockout hysteresis voltage v dd =v bs =sweep 0.6 v input logic section v ih logic ?1? input voltage for ho & logic ?0? for lo 2.5 v v il logic ?0? input voltage for ho & logic ?1? for lo 0.8 v i in+ logic input high bias current v in =5v, sd =0v 25 60 a i in- logic input low bias current v in =0v, sd =5v 3 a r in logic input pull-down resistance 200 k v sdclamp shutdown (sd ) input clamping voltage 5.0 5.5 v sd + shutdown (sd ) input positive-going threshold 2.5 v sd - shutdown (sd ) input negative-going threshold 0.8 v r psd shutdown (sd ) input pull-up resistance 200 k gate driver output section v oh high-level output voltage (v bias - v o ) no load 1.5 v v ol low-level output voltage no load 100 mv i o+ output high, short-circuit pulsed current (5) v ho =0v, v in =5v, pw 10s 2.0 2.5 a i o- output low, short-circuit pulsed current (5) v ho =15v,v in =0v, pw 10s 2.0 2.5 a v s allowable negative v s pin voltage for in signal propagation to ho -9.8 -7.0 v
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 dynamic electrical characteristics v bias (v dd , v bs )=15.0v, com=0v, c l =1000pf, and t a =25c, unless otherwise specified. note: 6. the turn-on propagation delay time included dead-time. symbol parameter conditions min. typ. max. unit t on turn-on propagation delay time (6) v s =0v 600 850 ns t off turn-off propagation delay time v s =0v 200 350 ns t sd shutdown propagation delay time 140 220 ns mt on delay matching, ho and lo turn-on 0 50 ns mt off delay matching, ho and lo turn-off 0 50 ns t r turn-on rise time v s =0v 25 50 ns t f turn-off fall time v s =0v 20 35 ns dt dead-time: lo turn- off to ho turn-on and ho turn-off to lo turn-on 300 400 500 ns mdt dead-time matching=|dt lo-ho - dt ho-lo | 0 50 ns
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 7 typical characteristics figure 4. turn-on propagation delay vs. temperature figure 5. turn-off propagation delay vs. temperature figure 6. turn-on rise time vs. temperature figure 7. turn-off fall time vs. temperature figure 8. turn-on delay matching vs. temperature fig ure 9. turn-off delay matching vs. temperature -40-20 0 20406080100120 400 450 500 550 600 650 700 750 800 t on [ns] temperature [c] -40-20 0 20406080100120 40 80 120 160 200 240 280 t off [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 0 10 20 30 40 50 t r [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 -10 0 10 20 30 t f [ns] temperature [c] -40-20 0 20406080100120 -20 -10 0 10 20 30 mt on [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 -20 -10 0 10 20 30 mt off [ns] temperature [c]
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 8 typical characteristics (continued) figure 10. dead-time vs. temperature figure 11. shutdown propagation delay vs. temperature figure 12. quiescent v dd supply current vs. temperature figure 13. quiescent v bs supply current vs. temperature figure 14. operating v dd supply current vs. temperature figure 15. operating v bs supply current vs. temperature -40-20 0 20406080100120 300 350 400 450 500 550 dt [ns] temperature [c] -40-20 0 20406080100120 50 100 150 200 250 300 t sd [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 250 300 350 400 i qdd [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 0 20 40 60 80 100 120 i qbs [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 200 400 600 800 1000 1200 i pdd [ a ] temperature [c] -40-20 0 20406080100120 0 200 400 600 800 1000 i pbs [ a ] temperature [c]
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 9 typical characteristics (continued) figure 16. v dd uvlo+ vs. temperature figure 17. v dd uvlo- vs. temperature figure 18. v bs uvlo+ vs. temperature figure 19. v bs uvlo- vs. temperature figure 20. high-level output voltage vs. temperature figure 21. low-level output voltage vs. temperature -40 -20 0 20 40 60 80 100 120 8.0 8.5 9.0 9.5 10.0 v dduv+ [v] temperature [c] -40 -20 0 20 40 60 80 100 120 7.5 8.0 8.5 9.0 9.5 v dduv- [v] temperature [c] -40 -20 0 20 40 60 80 100 120 8.0 8.5 9.0 9.5 10.0 10.5 v bsuv+ [v] temperature [c] -40 -20 0 20 40 60 80 100 120 7.0 7.5 8.0 8.5 9.0 9.5 10.0 v bsuv- [v] temperature [c] -40 -20 0 20 40 60 80 100 120 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v oh [v] temperature [c] -40 -20 0 20 40 60 80 100 120 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 v ol [v] temperature [c]
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 10 typical characteristics (continued) figure 22. logic high input voltage vs. temperature figure 23. logic low input voltage vs. temperature figure 24. logic input high bias current vs. temperature figure 25. allowable negative v s voltage vs. temperature . -40 -20 0 20 40 60 80 100 120 1.0 1.5 2.0 2.5 3.0 v ih [v] temperature [c] -40 -20 0 20 40 60 80 100 120 0.5 1.0 1.5 2.0 2.5 3.0 v il [v] temperature [c] -40 -20 0 20 40 60 80 100 120 0 10 20 30 40 50 i in+ [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 -13 -12 -11 -10 -9 -8 v s [v] temperature [c]
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 switching time definitions figure 26. switching time test circuit figure 27. input/output timing diagram figure 28. switching time waveform definition +15v sd 10uf 100nf 1nf 1nf +15v 100nf 10uf ho lo lo com v b v s v dd sd in 7 ho 6 5 2 3 1 4 8 in ho lo sd dt1 dt2 dt1 dt2 dt1 shutdown shutdown dt2 dt1 dt2 in ho lo 10% 90% 50% 50% 90% 10% t off 10% 90% t r t r 10% 90% t r t f t off t on t on
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 figure 29. shutdown waveform definition figure 30. dead-time waveform definition figure 31. delay matchi ng waveform definition 90% 50% t sd ho or lo sd mdt= dt lo-ho - dt ho-lo ho lo 10% 90% 90% 10% t off dt lo-ho dt ho-lo in 50% 50% t off 50% 50% in(ho) 90% 90% 10% 10% in(lo) mt on mt off ho lo 50% 50%
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 ? rev. 1.0.1 mechanical dimensions figure 32. 8-lead small outline package (sop) package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 8 0 see detail a notes : unles s otherwi se specifie d a) this p ackage confo rms to jedec ms-012, varia ti on aa, iss ue c, b ) al l dimensio ns are i n mil limete rs . c) dimensions do not include mold flash or b urrs. d) landpattern standard: soic127p600x175-8m. e) dra wing fi lename: m0 8a re v13 land pattern recommendation se ati ng p l ane 0.1 0 c c ga ge plane x 45 detail a sc al e: 2: 1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) op tion a - b ev el e dge o pti on b - no be ve l edg e
fan73932 ? half-bridge gate drive ic ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan73932 rev. 1.0.1 14

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